1. Field of the Invention
The present invention primarily relates to a semiconductor memory device having a memory cell array configured by arranging a plurality of memory cells that include a variable resistance element for storing information based on an electrical operation characteristic in which the electrical resistance varies due to the application of electrical stress, in a row direction and a column direction, respectively.
2. Description of the Related Art
A non-volatile memory represented by a flash memory is used as a large-capacity and small-size information recording medium in vast areas including computers, communications, measurement instruments, automatic control devices, and household appliances used around individuals, and the demand for a inexpensive non-volatile memory with large capacity is extremely high. This is due to reasons that since a non-volatile memory can be electrically written and data thereof is not erased even when the power supply is turned off, the non-volatile memory can exhibit the functions of an easily portable memory card, cell phone, or data storage and program storage that stores data in a non-volatile manner as the default settings for device operation.
However, a flash memory cannot perform high-speed operations since the erasing action in which the data is erased at a logical value “1” consumes more time period, as compared to a programming action in which the data is written at a logical value “0”. As regards the erasing action, although an improvement in speed can be achieved by performing the erasing action in a block unit, there still exists a problem that erasure performed in the block unit does not allow writing to be performed through random access.
Therefore, currently, as an alternative to the flash memory, new types of non-volatile memory are being researched extensively. Among these, a resistance-change memory using the phenomenon of occurrence of a resistance change due to the application of electric voltage on a metal oxide film is more beneficial as compared to a flash memory from the viewpoint of the miniaturization limit, and furthermore, due to the capability of low-voltage operation and high-speed data writing, recently its research and development are being performed increasingly.
A writing characteristic (programming and erasing characteristic) of a variable resistance element having these metal oxides is that in the case of a drive method called bipolar switching, when a voltage pulse is applied on the element in a reversed polarity in the programming action and the erasing action, respectively, the electrical resistance of the element either increases (converts to high resistance) or decreases (converts to low resistance) in accordance with the polarity of the voltage pulse, and as a result, by applying a logical value as data to each electrical resistance state, the variable resistance element can be used as a memory element.
A characteristic of the memory device using the variable resistance element having the metal oxide is that since both the programming action and the erasing action can be performed with a high speed at low voltage, high-speed writing is possible for arbitrary address. Therefore, since the data, which has conventionally been used after being developed in a DRAM, can be used in a non-volatile memory, such a memory device is expected to make a great contribution to the reduction of power consumption and improvement in usability of mobile devices. On the other hand, there are unresolved problems resulting from the driving methods specific to bipolar switching.
In order to write a precise resistance value as the storage information in a variable resistance element, and to improve the reliability of a memory element, it is preferable to repeatedly perform a writing action for changing the electrical resistance of the variable resistance element in a selected memory cell, and a reading action (verifying action) for verifying the resistance value that has been written. According to the verifying action, after a voltage pulse for the writing action has been applied to the variable resistance element in the selected memory cell, a voltage pulse for the verifying action is applied, and by detecting, by a sense amplifier, the electric current flowing in the selected memory cell or the voltage variation owing to the electric current and the like, it is verified as to whether or not the electrical resistance of the variable resistance element caused by the writing action has changed up to a desired resistance value (for example, see JP 2009-99199 A). For convenience of explanation below, it is assumed that a memory cell array is formed by arranging a plurality of memory cells in the row direction and the column direction, respectively, and while every one end of the memory cells in the same column is connected to a common bit line, every other end of all memory cells is connected to a common source plate. It is to be noted that the problem explained below is the same even for an array configuration in which every other end of the memory cells in the same row or the same column is connected to a common source line.
Conventionally, because the normal reading action for the memory cells that have already been written, and the verifying action are both performed by using the same sense amplifier, each action is executed by applying a voltage pulse of the same polarity. Therefore, when the writing action is performed based on the bipolar switching action, even if the polarity of the voltage pulse applied to the variable resistance element is different between the writing action for converting the resistance state of the variable resistance element to a low resistance (hereinafter, referred to as the “setting action”), and the writing action for converting the resistance state of the variable resistance element to a high resistance (hereinafter, referred to as the “resetting action”), the polarity of the voltage pulses applied to the variable resistance element during the verifying actions for these is the same.
In the setting action, if it is determined that the electrical resistance of the variable resistance element is not sufficiently converted to a low resistance during the verifying action after the setting action, a repeated setting action is executed. The verifying action is performed for the repeated setting action as well, and until it is determined that the electrical resistance of the variable resistance element has been sufficiently converted to a low resistance, or until the frequency of the repeated setting action reaches the prescribed frequency, the repeated setting action and its verifying action are repeated. If the polarity of the voltage pulse applied to the variable resistance element is the same between the setting action and its verifying action, the electric potential of the source plate and an unselected bit line may be retained as the reference electric potential and need not be changed, during the repetitive action.
Even in the resetting action, similar to the setting action, if it is determined that the electrical resistance of the variable resistance element is not sufficiently converted to a high resistance during the verifying action after the resetting action, a repeated resetting action is executed. The verifying action is performed for the repeated resetting action as well, and until it is determined that the electrical resistance of the variable resistance element has been sufficiently converted to a high resistance, or until the frequency of the repeated resetting action reaches the prescribed frequency, the repeated resetting action and its verifying action are repeated. As described above, if the polarity of the voltage pulse applied to the variable resistance element is the same between the setting action and its verifying action, the polarity of the voltage pulse applied to the variable resistance element is different between the resetting action and its verifying action. As a result, each time a resetting action is performed, the source plate and the unselected bit line must be precharged to a predetermined reset electric potential, and each time a verifying action is performed, the electric potential of the source plate and the unselected bit line must be discharged to the reference electric potential. As described above, every time the repeated resetting action and its verifying action are repeated, the precharging and discharging are also repeated for the source plate and the unselected bit line. Although the size of the source plate depends on the array size, the total wiring length might be long (the total area is large when the source plate is formed on a plane surface), and the source plate might have a parasitic capacitance of a few 100 pF. Even the total wiring length of the unselected bit line depends on the total number of bit lines, however, generally, since the number of unselected bit lines is extremely large than the number of selected bit lines, unselected bit lines occupy a considerable proportion of the total bit-line wiring length, and might have a parasitic capacitance of a few 100 pF, similar to a source plate. As a result, by charging and discharging such a large parasitic capacitance, the power consumption during the resetting action increases, which poses a problem. Additionally, if such a large parasitic capacitance is charged rapidly, a large spike noise occurs in the power supply potential because of which precharging cannot be performed at a high speed, and the time period of the resetting action increases, thus posing a problem. Particularly, when the predetermined reset electric potential is to be generated in an internal booster circuit, it becomes necessary to sufficiently control the output current of the driver that drives the reset electric potential such that the current supply capability of the booster circuit is not exceeded. These are the factors that cause a decline in the throughput of the repetitive action in the resetting action.
When the polarity of the voltage pulse applied to the variable resistance element is the same between the setting action and its verifying action, then as described above, the problems of increased power consumption and occurrence of noise are seen in the resetting action. Conversely, when the polarity of the voltage pulse applied to the variable resistance element is the same between the resetting action and its verifying action, the aforementioned problems of increased power consumption and occurrence of noise are seen in the setting action.